The present invention relates to inkjet printheads. In particular, it relates to a heater chip thereof having reduced size due to narrowed-width power FETs driven by an integral voltage regulator with regulating capacitors.
The art of printing images with inkjet technology is relatively well known. In general, an image is produced by emitting ink drops from an inkjet printhead at precise moments such that they impact a print medium at a desired location. The printhead is supported by a movable print carriage within a device, such as an inkjet printer, and is caused to reciprocate relative to an advancing print medium and emit ink drops at such times pursuant to commands of a microprocessor or other controller. The timing of the ink drop emissions corresponds to a pattern of pixels of the image being printed. Other than printers, familiar devices incorporating inkjet technology include fax machines, all-in-ones, photo printers, and graphics plotters, to name a few.
Conventionally, a thermal inkjet printhead includes access to a local or remote supply of color or mono ink, a heater chip, a nozzle or orifice plate attached to the heater chip, and an input/output connector, such as a tape automated bond (TAB) circuit, for electrically connecting the heater chip to the printer during use. The heater chip, in turn, typically includes a plurality of thin film resistors or heaters fabricated by deposition, masking and etching techniques on a substrate such as silicon.
To print or emit a single drop of ink, an individual resistive heater is uniquely addressed with a small amount of current to rapidly heat a small volume of ink. This causes the ink to vaporize in a local ink chamber (between the heater and nozzle plate) and be ejected through and projected by the nozzle plate towards the print medium.
The circuitry that drives the printing of a single ink drop typically includes a source of a field effect transistor (FET) and a voltage source (+10.8 volts is common) coupled to either ends of the resistive heater. Control logic circuitry sends logic signals to a gate of the FET and, upon actuation of the FET, the resistive heater heats and ink is ejected.
As a natural occurrence of powering transistor-transistor logic (TTL) devices of the control logic circuitry with +5 volts, many FETs are driven with the same voltage. With present day CMOS ASICs, however, the voltage standard for control logic is +3.3 volts. Thus, if a heater chip of an inkjet printer is to power its CMOS with one voltage and drive its FET with another voltage, while providing powering voltage of its resistive heaters with still another voltage, at least three different voltages need to be conveyed from the printer to the heater chip and must, in turn, be laid out (wired) feasibly on the chip. This, however, adds circuit cost and complexity.
Accordingly, the inkjet printhead arts desire heater chips having optimum voltage control without attendant chip expense.
The above-mentioned and other problems become solved by applying the apparatus and method principles and teachings associated with the hereinafter described inkjet printhead heater chip having reduced size.
In one embodiment, the heater chip has an integral voltage regulator that derives two output voltages from a single voltage input to the chip. One of the two output voltages powers control logic circuitry while the other powers FET drivers. Preferably, the input voltage includes +10.8 volts and the output voltages include lines of +3.3 volts for the control logic circuitry and +7.5 volts for the FET drivers. A Vgs of the FET is about +7.5 volts which enables a FET area width of about 400 microns and an area length of about 42 microns ({fraction (1/600)}th inch). Outputs of the control circuitry provide input to the FET drivers. A resistive heater for ejecting ink couples between a drain of the FET and the chip input voltage. Preferred FET drivers include logic AND gates or logic NAND gates with an inverter.
In another aspect of the invention, voltage regulating capacitors exist on the heater chip in parallel with either or all of the input voltage and each of the output voltages. Preferred capacitors have a gate oxide and a polysilicon layer overlying a substrate and may or may not have a region of n-well doping within the substrate beneath the gate oxide. The positive capacitor electrode attaches to the polysilicon layer. The negative capacitor electrode attaches to an electrically grounded substrate.
Printheads containing the heater chip and printers containing the printhead are also disclosed.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in the description which follows, and in part will become apparent to those of ordinary skill in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.